Combined Distributed Shared-Buffered and Diagonally-Linked Mesh Topology for High-Performance Interconnect
Networks-on-Chip (NoCs) have become the de-facto on-chip interconnect for multi/manycore systems.A typical NoC router is made up of buffers used to store packets that are unable to advance to their desired destination.However, buffers consume significant power/area and are often underutilized, especially in cases of applications with non-uniform tr